At this year's North American RISC-V Summit, the unofficial motto was "drain the swamp," meaning that RISC-V will be an alternative to x86 and ARM, regardless of device or computing environment. 

At the Santa Clara conference, there were some big promises about the upcoming instruction set architecture.

Meta and Qualcomm said the RISC-V architecture is central to their chip development programs. Company executives also opened the door to making major computing chips using the architecture.

RISC-V is still young, and it will be years, if not decades, before it replaces x86 or ARM. But it has a lot going for it. 

The architecture is free to license, which lowers the barrier to entry and cost. It also has a flexible design that brings more computing power to modern workloads.

Meta and Qualcomm's commitment also highlights a sobering reality - companies are willing to give up proprietary technology.

"The market is ready and eager for choice. They don't want to be locked into a proprietary roadmap. They want choices, and the freedom of choice has expanded." Calista Redmond, CEO of RISC-V International, said in a chat with HPCwire.

RISC-V can be a quasi-system scheduler or a fully loaded processor, depending on the customer's needs. It can be adapted to newer computing models around sparse computing, where data is closer to the processing core.

Here are some observations from the two-day event, now in its sixth year.

Attendees at the RISC-V Summit were both excited and disturbed by the U.S. government's interest in taming the open standard.

On the one hand, RISC-V came out of obscurity and into the big leagues by attracting government attention. But the idea of Joe Biden's administration interfering in RISC-V standard-setting was met with widespread opposition.

Participation and interaction have begun, and the atmosphere in the exhibit hall is one of sharing ideas and collaborating to improve the RISC-V architecture.

RISC-V is following in the footsteps of global standards such as Ethernet, USB and HTTPS, which have spurred technological innovation. Short-circuiting RISC-V development can be disastrous and can discourage choice and innovation, Redmond said. 

"Proprietary models are a much bigger trap for geopolitical issues than open architectures. I think some of the rhetoric you hear doesn't really realize that," Redmond said.

The U.S. government's prying eyes on RISC-V didn't stop Chinese company Alibaba from attending the summit and showing off products based on the instruction set architecture. 

In fact, on U.S. soil, Alibaba did even better - the company announced a 3,072-core RISC-V server built on a chip made in China. The server, which has 48 nodes and is powered by a 64-bit Sophon SG2042 chip, has been deployed at Shandong University in China.

Alibaba claims the server is the first commercially deployed RISC-V server. There are no known RISC-V server deployments in U.S. cloud services.

At first glance, China is way ahead of the US in the RISC-V race.

China has a concerted program to develop domestic RISC-V based chips. The government is funding university students and startups to develop chips, while the U.S. fumbles with what to do about RISC-V.

Concerns about restricting U.S. companies from working with China on RISC-V were not mentioned in the keynote. Instead, the speaker talked about the borderless nature of the RISC-V architecture, with almost equal participation from all regions.

There are currently estimated to be about 10 billion RISC-V cores on the market, and a study by the SHD Group suggests that by 2030, about 18 billion RISC-V chips will have been shipped.

Of the 18 billion chips, microcontrollers top the list, totaling more than 6.5 billion, followed by AI gas pedals at 4 billion, networking chips at 2 billion, security chips at a little over 1.1 billion, and general-purpose CPUs at about 900 million. 

Qualcomm has shipped more than 1 billion devices with integrated RISC-V cores to date. The company is using RISC-V controllers for the first time in Snapdragon 865 chips in 2019 and will be expanding the instruction set architecture across all product lines.

The SHD Group's research was funded by RISC-V, so we take it with a grain of salt. But it's the only estimate that quantifies future RISC-V shipments, conducted by a well-known researcher, researcher Rich Wawrzyniak.

RISC-V cannibalizes other RISCs

RISC-V is a juggernaut for other RISC designs and forgotten architectures along the way.

For starters, RISC-V this week used the ARC architecture, a RISC-based design that dates back decades when it was introduced into the SuperFX chips used in the Super Nintendo system.

Synopsys is behind the ARC-V processor, which has now transitioned to the RISC-V architecture, which is still supported by older versions of ARC, and MIPS, which previously transitioned completely to RISC-V after abandoning the old architecture.

Redmond said the convergence of other RISC architectures to RISC-V is entirely dependent on strength of numbers. 

Redmond said, "Your secret sauce is your implementation and the ability to accelerate the development community in to bring their workloads and applications into it."

Security is still not a first-class citizen in RISC-V design. Companies insist that their RISC-V chips have security layers, cryptographic extensions, etc., but that's still the bare minimum.

RISC-V chips are still not ready for applications such as classified computing, where security enclaves protect code or applications and can only be accessed by authorized entities.

The concept of security by design is gradually permeating chip developers. With the TDX extension, Intel and AMD and their SEV-SNP capabilities can build strong security into the CPU. Intel's new APX feature also reduces branch prediction, thereby reducing the attack surface for hackers.

A number of security-focused vendors were also in the exhibit hall at the RISC-V Summit. Emproof, headquartered in Germany, has a security layer that sits behind the compiler, obfuscating binary code and protecting it from reverse engineering. The company has received interest from RISC-V companies looking to protect on-chip functionality. 

LowRISC, based in Cambridge, UK, has developed a root of trust that protects chips from firmware and other on-chip attacks based on OpenTitan, an open-source version of the Titan chip's root of trust that Google uses to protect its devices.

One of the biggest winners was Ventana Microsystems, which released a 192-core RISC-V CPU core called Veyron V2. The chip pushes the limits of RISC-V processors and matches x86 and ARM with the latest interconnects, memory technologies and small chip implementations.

The new chip will be 40 percent faster than the Veyron V1 released a year ago. It also supports the upcoming UCIe interconnect, which is also supported by other major x86 and ARM chip makers. 

It supports the latest vector extensions recently approved by RISC-V International, which were not in V1. V2 has more enhancements in the microarchitecture and pipeline.

Balaji Bakhta, CEO of Ventana Micro Systems, told HPCwire, "Basically, we are achieving parity with ARM or x86 at the system IP level."  

The Veyron V2 will be manufactured on a 4-nanometer process, which is an improvement over the V1's 5-nanometer process. 

Bakhta said high-performance computing companies are interested in the chip. The systems will be delivered to customers next year, Bakhta said.