The world's largest international conference on semiconductor device technology and process technology, IEDM (International Electron Devices Meeting), will be held from December 9 to 13, 2023 in San Francisco, California, USA. At the conference, a series of future memory technologies will be announced, let's take a look.

The field of "memory" is a particularly hot topic this year. Unlike in the past, the number of research publications on DRAM technology has increased significantly. Last year at IEDM 2022, there were so few "Notable DRAM Presentations" that they did not even make it into the list. This year, however, the number has increased to the point where it would take three lists to present notable talks. It is worth noting that the number of notable talks reached nine.

In addition, I was surprised to find that there are still active research publications on crosspoint memories targeting high-capacity nonvolatile memories. This is because Intel and Micron Technology ("Micron") have withdrawn from 3D XPoint memory, and it is thought that the research enthusiasm has cooled down.

In the following, we will introduce "DRAM," "3D NAND flash memory," "XPoint memory," "Magnetoresistive memory ("MRAM")," and "Magnetic Resistive Memory ("MRAM"). DRAM", "3D NAND Flash", "XPoint Memory", "Magnetoresistive Memory ("MRAM")", and "Ferroelectric Memory ("FRAM")".

Regarding next-generation DRAM cell technology, the results of reducing cell area to 4F2 have been announced. Here, "F2" represents the square of the design rule "F" (corresponding to the minimum processing size), and "4" represents four times F2. In principle, the memory cell area can be reduced by up to two-thirds compared to the 6F2 cell currently used in large-capacity DRAM.

Samsung Electronics (hereinafter referred to as Samsung) has developed self-aligned tri-gate FET/GAA FET technology, which is future-proof and based on 4F2 DRAM cell technology (Presentation No. 6-1).

Storage fabs from China and other joint research groups will announce high-performance, low SS GAA junctionless vertical channel transistor (VCT) technology for next-generation 4F2 DRAM cells (6-2). The capacitor is a positive hexagonal columnar stack type.

Samsung has also developed single-gate IGZO vertical channel transistor (VCT) technology (6-3) for sub-10nm generation 4F2 DRAM cells. Cell arrays are monolithically stacked on top of the core and peripheral circuits.

As the DRAM technology node moves to the next generation beyond 10nm, area reduction using 4F2 cells is nearing its limits. 3D DRAM cells are a powerful alternative. By eliminating the need for capacitors, density can be more easily increased through three-dimensional stacking. It is also referred to as a "2T0C cell" because a cell typically consists of two transistors.

Macronix International (hereinafter referred to as Macronix) has developed capacitorless 3D DRAM technology using gated thyristors and a crossbar structure. Shorter cell spacing and improved signal sensing make it easier to increase the number of layers in the crossbar structure.

Samsung will announce a capacitorless DRAM technology called "3-STAR" (6-6). Stackable transistor arrays (specifically, it appears to be thyristor arrays) are used as DRAM cell arrays.

In addition, the Institute of Microelectronics, Chinese Academy of Sciences (IMCAS) will be releasing three and many other capacitorless DRAM technologies using vertical channel transistors (VCTs) with IGZO as the channel material. One is a monolithic stacked single gate IGZO vertical channel transistor technology (Demo No. 6-7), another is a dual transistor/cell technology with two layers of IGZO channels, and a third The third is dual-gate IGZO, which is a multi-bit DRAM cell technology using transistors.

On "3D NAND Flash Memory," Samsung will give an invited talk on the challenges of realizing high-density 3D NAND flash memory with more than 1,000 stacked cell transistor layers.

A joint research team from Kioxia and Western Digital (WD) described a wafer bonding technology for 3D NAND flash memory that achieves high input/output speeds of 3.2 Gbps and high-speed write throughput of 205 MB/s. This is an essential part of the next generation of 3D NAND flash memory. This is the basic technology for the next generation of 3D NAND flash memory, which the two companies call "BiCS8 (8th generation).

Samsung has also presented design guidelines for QLC (4-bit/cell) type 3D NAND flash memory, which incorporates ferroelectric FETs for charge trapping.

In "Crosspoint Memory," Samsung will present the results of prototyping a 64Gbit high-capacity non-volatile memory cell array using only the OTS (ovonic threshold switch) selector, which has a very short size of 16nm square. Read access time is 56ns (destructive read). Read cycle life is 109 cycles and write cycle life is 108 cycles.

Micron will explain the current state of 3D crosspoint storage technology and look to the future in an invited talk. This is also a highly anticipated talk as it will be the first time that developers will be able to provide an overview of 3D XPoint, a cross-point storage technology based on sulfur compounds.

TSMC will demonstrate low-voltage, long-life, high-density embedded memory technology using a selector and an STT-MRAM. The selector is a SiNGeCTe composite threshold switch. The rewrite cycle life is 1 million cycles. Supply voltage is very low, less than 1.8V.

Regarding "Magnetoresistive Memory (MRAM) Technology", Avalanche Technology has developed a high-capacity 8Gbit STT-MRAM with improved radiation resistance for space use. Long-term reliability is high, with a data retention period of more than 10 years at 125°C and a rewrite cycle life of more than 10 to the 14th power.

Kioxia has prototyped a magnetic tunnel junction (MTJ) for the 1Znm generation of high-speed STT-MRAM using 14nm technology. The write time is very short at 5ns. The data retention period is more than 10 years at 90°C. imec has investigated the miniaturization of multi-column MRAM using gate voltage controlled spin-orbit torque (VGSOT). The intended use is for last level cache (LLC). It is said that it can be scaled down to 1.4nm node (14A node).

With regard to "ferroelectric memory," a joint research group including Sony Semiconductor Solutions has produced a prototype of a 1Mbit ferroelectric nonvolatile RAM with a 1T1C cell.

A joint research group including TSMC and others will introduce a ferroelectric FET using the two-dimensional material molybdenum difluoride (MoS2) as the channel material, which is suitable for embedded memory. It is assumed that the cycle life will be extended by using 2D materials. Data retention period is more than 10 years. The gate insulating film is HZO layer and AlOx layer. When the thickness of the HZO layer is 2.5 nm and MoS2 is a single layer, the write voltage can be reduced to 1.0 V or less.