A few years ago, Lightmatter made a splash by demonstrating Mars, an artificial intelligence gas pedal that rethinks the paradigm of electronic computing and mobile data. They demonstrated a processor that uses photonics for computation. The chip promises to increase latency, bandwidth and power by multiple orders of magnitude. This was ultimately unsuccessful due to the rigidity of the software and computational architecture involved in the chip.

Lightmatter has created a second generation AI computing product called Envise, but that is not the focus of today's post. We wanted to share what Lightmatter is showing on their latest product, Passage. To summarize, with Passage Lightmatter wants to break the limits of advanced packaging and IO.

It is well known that problem sizes in areas like AI and HPC are growing exponentially, but Moore's Law can't keep up.

As a result, the industry has turned to using chiplets to combine larger packages to continue to meet computing demands. Breaking the chip into many chiplets and exceeding the scalar limit (the physical limit of the patterning limit of lithography tools) will enable continuous scaling, but this paradigm is still problematic. Even with advanced packaging, the cost of power to move data off the chip will be a limiting factor. In addition, even with the most advanced forms of packaging, bandwidth would still be limited.

Instead of putting silicon on silicon, Lightmatter wants to disrupt the advanced packaging game with Passage, which connects to 48 customer chips on an optically mediated layer. passage is built on top of GlobalFoundries Fotonix 45CLO process technology. It is designed to connect many chips at very high bandwidth and performance. This optical interposer breaks bandwidth limitations by providing 768 terabits per second between each tile and can scale to multiple interposers at 128 terabits per second, a level of capability and scale unattainable with traditional packaging.

For decades, optics has promised to solve the bottleneck of electrical IO. Technology has been slow to advance in this area, and pluggable optics, which Lightmatter calls Gen 1, have been used for years to connect switches within data centers. Thanks to companies like Intel and Ayar Labs, Gen 2 and Gen 3 optics (which put optics on the same package or connect directly) are starting to enter the network switch and computing space. lightmatter wants to jump straight to Gen 4 and Gen 5 with Passage.

Standard co-packaged optics such as Intel and Ayar Labs scale an order of magnitude lower than the optical intermediary layer solution used by Lightmatter. The interconnect density is 40 times higher because only about 200 fibers can be inserted into a single chip. In addition, the interconnect is completely static, while Passage has a dynamically configurable structure.

This optical intermediary layer allows switching and routing between chips. The entire interconnect can be reconfigured in less than 1ms.

Lightmatter says they can support all topologies such as all to all, 1D ring, Torus, Spine and Leaf, etc. Passage's switching and routing has a maximum latency of 2ns between any chip on a 48-chip array and any other chip.

Switching is achieved by modulating the colors using ring resonators and directing them using a Mach-Zender interferometer.

Lightmatter's photonic wafer-level intermediary layer has A0 silicon and claims to use less than 50 watts of power per site. Each site has 8 hybrid lasers driving 32 channels; each channel runs 32Gbps NRZ.

Lightmatter's wafer-scale silicon photonic chip is primarily based on silicon-based manufacturing technology; it has many of the same limitations. GlobalFoundries and Lightmatter have solved this problem by stitching the waveguide. The photomask-to-mask connection of the nanophotonic waveguide has a loss of only 0.004 dB at each mask crossing. The waveguide loss is 0.5 dB/cm and the loss per Mach-Zehnder interferometer is 0.08 dB. There is also a loss of 0.028 dB per crossover.

Lightmatter says that with UCIe, they can run the highest specification 32Gbps chiplet-to-interposer interconnect. With direct SERDES, they believe they can run at 112G. The customer ASIC is 3D encapsulated on top of the interposer layer. OSAT will then assemble this final product. It can come in many variants, from 48 chips to a smaller interposer with only 8 chips. the passage package must also power the chip that is packaged on top. It does this by using TSV to provide up to 700W of power per tile. Water cooling is required at this power level, but if the customer ASIC consumes less, they can use air cooling.

Note that the claimed 768Tbps seem to be largely wasted. Their functionality seems to allow them to couple one input to one output. This leaves most of the interconnects idle. This will be necessary in order for them to find paths that do not conflict. These paths are passive and waste little power when not in use. mzi elements to the left or to the right. There is no blending, no multicasting. One in, one out.

Lightmatter also gave an example of a decomposed memory design and multi-tenant architecture. They started their interposer to support any protocol, including CXL. The customer ASICs on top of the interposer could implement air gaps by reconfiguring the network so that passing data between specific chips was not possible. The big question is if and when the product will be available. This could be just vaporware, or it could be the future of high-end leading edge classified server designs. lightmatter must attract other companies to build chips for this platform. These companies will have to put their expensive development trust with unproven partners.