There are so many types of packages in the world of chips, here is a summary of more than 70 common chip packages. I hope this will give you a general understanding of packaging.

1、BGA(ball grid array)

Ball contact display, one of the surface mount type package. In the back of the printed substrate according to the display way to make a ball bump to replace the pins, in the front of the printed substrate assembly LSI chip, and then sealed with molding resin or potting method. This is also called a bump display carrier (PAC). It can have more than 200 pins and is a type of package used for multi-pin LSI. 

The package body can also be made smaller than a QFP (quad side pin flat package). For example, a 360-pin BGA with 1.5mm pin centers is only 31mm square, while a 304-pin QFP with 0.5mm pin centers is 40mm square. And BGAs do not have to worry about pin deformation as QFPs do. The package was developed by Motorola in the U.S. and was first adopted in devices such as portable phones, and is likely to become popular in the U.S. for personal computers in the future.

Initially, BGAs had 1.5 mm pin (bump) centers and 225 pins, and some LSI manufacturers are now developing 500-pin BGAs. It is not clear if there is a valid inspection method. Some believe that the connection can be considered stable due to the large center distance of the solder and can only be handled by functional inspection. Motorola USA refers to packages sealed with molded resin as OMPAC and those sealed by potting methods as GPAC (see OMPAC and GPAC).

2、BQFP(quad flat package with bumper)

A quad flat package with bumper, one of the QFP packages, has bumps (bumper pads) at the four corners of the package body to prevent the pins from bending and deforming during shipping. U.S. semiconductor manufacturers use this package mainly for circuits such as microprocessors and ASICs. The pin center distance is 0.635 mm and the number of pins ranges from 84 to about 196 (see QFP).

3、PGA (butt joint pin grid array)

An alias for surface mount PGAs (see surface mount PGAs).

4、C-(ceramic)

The mark of ceramic package. For example, CDIP means ceramic DIP, which is often used in practice.

5、Cerdip

Cerdip is a ceramic double in-line package sealed with glass, used for ECL RAM, DSP (Digital Signal Processor) and other circuits. Cerdip with a glass window is used for UV-erasable EPROMs and microcomputer circuits with EPROMs inside, etc. The pin center distance is 2.54mm and the number of pins is from 8 to 42. In Japan, this package is called DIP-G (G means glass sealed).

6、Cerquad

One of the surface-mount packages, the ceramic QFP with an under-seal, is used to package logic LSI circuits such as DSPs. Cerquad with a window is used to package EPROM circuits. It has better heat dissipation than plastic QFPs and can accommodate 1.5 to 2W of power under natural air cooling conditions. However, the package cost is 3 to 5 times higher than the plastic QFP. The pin center distance is 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, etc. The number of pins ranges from 32 to 368.

7、CLCC(ceramic leaded chip carrier)

Ceramic leaded chip carrier with pins, one of the surface mount package, the pins are led from the four sides of the package, in the shape of a ding. The window is used to package UV erasable EPROMs and microcomputer circuits with EPROMs. This package is also known as QFJ, QFJ-G (see QFJ).

8、COB(chip on board)

Chip on board package is one of the bare chip mounting technology, semiconductor chip is mounted on the printed circuit board, the electrical connection between chip and substrate is realized by lead stitching method, the electrical connection between chip and substrate is realized by lead stitching method, and it is covered with resin to ensure reliability. Although COB is the simplest bare chip mounting technology, but its package density is far inferior to TAB and inverted chip soldering technology.

9、DFP(dual flat package)

Double side pin flat package. It is the alias of SOP (see SOP). Used to have this name, but now it is basically not used.

10、DIC(dual in-line ceramic package)

Ceramic DIP (with glass seal) alias (see DIP).

11, DIL (dual in-line)

DIP alias (see DIP). European semiconductor manufacturers mostly use this name.

12、DIP(dual in-line package)

Double in-line package. One of the cartridge package, the pins are led from both sides of the package, the package material has two kinds of plastic and ceramic . DIP is the most popular cartridge package, the application range includes standard logic IC, memory LSI, microcomputer circuits, etc.. 

The pin center distance is 2.54mm and the number of pins ranges from 6 to 64. The package width is usually 15.2mm, and some packages with a width of 7.52mm and 10.16mm are called skinny DIP and slim

DIP (narrow body DIP) respectively. Also, ceramic DIPs sealed with low melting point glass are called cerdip (see cerdip).

13、DSO(dual small out-lint)

Double side pin small outline package, an alias for SOP (see SOP). Some semiconductor manufacturers use this name.

14、DICP(dual tape carrier package)

One of the TCP (tape carrier package). The pins are made on the insulating tape and lead out from both sides of the package. Due to the use of TAB (automatic tape carrier soldering) technology, the package profile is very thin. It is commonly used for LCD driver LSIs, but most of them are custom-made. In addition, a 0.5mm thick memory LSI booklet package is under development. In Japan, the DICP is named DTP according to the EIAJ (Electronic Industries and Machinery of Japan) Association standard.

15、DIP(dual tape carrier package)

Same as above. The name of DTCP in the EIAJ (Japan Electronics Machinery Industry Association) standard (see DTCP).

16、FP(flat package)

Flat package. An alias for QFP or SOP (see QFP and SOP), one of the surface mount packages. Some semiconductor manufacturers use this name.

17、flip-chip

Flip-chip. One of the bare-chip packaging technologies in which a metal bump is made in the electrode area of the LSI chip and then the metal bump is pressure-soldered to the electrode area on the printed substrate. The area occupied by the package is basically the same as the size of the chip. It is the smallest and thinnest of all packaging technologies. However, if the coefficient of thermal expansion of the substrate is different from that of the LSI chip, it can react at the joint and affect the reliability of the connection. Therefore, it is necessary to reinforce the LSI chip with resin and to use a substrate material with approximately the same coefficient of thermal expansion.

18、FQFP(fine pitch quad flat package)

A QFP with a small pin center distance, usually less than 0.65mm (see QFP). Some conductor manufacturers use this name.

19、CPAC (globe top pad array carrier)

The alias for BGA (see BGA) from Motorola, USA.

20、CQFP(quad fiat package with guard ring)

Quad fiat package with guard ring. One of the plastic QFPs, the pins are masked with a protective resin ring to prevent bending and deformation. Before assembling the LSI on the printed substrate, the pins are cut from the guard ring and made into a seagull wing shape (L shape). This package is in mass production at Motorola in the US. The pin center distance is 0.5mm, and the maximum number of pins is about 208.

21、H-(with heat sink)

Indicates a mark with heat sink. For example, HSOP indicates SOP with heat sink.

22、pin grid array(surface mount type)

The surface mount type PGA is usually a cartridge type package with a pin length of about 3.4mm. surface mount PGA has a display of pins on the bottom side of the package with a length from 1.5mm to 2.0mm. the mounting is done by bump soldering to the printed substrate, so it is also called bump soldering PGA.

Since the pin center distance is only 1.27mm, which is half of that of the cartridge type PGA, the package body can be made smaller, and the number of pins is more than that of the cartridge type (250-528), so it is a package for large-scale logic LSI. The package substrates are multilayer ceramic substrates and glass epoxy printed substrates. The multilayer ceramic substrate has been used to make the package.

23、JLCC(J-leaded chip carrier)

J-shaped pin chip carrier. Refers to the windowed CLCC and windowed ceramic QFJ alias (see CLCC and QFJ). The name used by some semi-conductor manufacturers.

24、LCC(Leadless chip carrier)

Pinless chip carrier. It refers to the surface mount type package in which only the electrodes on the four sides of the ceramic substrate are in contact without pins. It is a package for high speed and high frequency ICs, also known as ceramic QFN or QFN-C (see QFN).

25、LGA(land grid array)

Contact display package. This is a package with an array of land electrode contacts on the bottom side. When assembled, it can be inserted into the socket. Ceramic LGAs with 227 contacts (1.27mm center distance) and 447 contacts (2.54mm center distance) are now in use for high-speed logic LSI circuits. 
LGAs can accommodate more input and output pins in a smaller package than QFPs. In addition, due to the low resistance of the leads, it is suitable for high-speed LSI. However, due to the complexity and high cost of making sockets, they are not used much now. The demand for them is expected to increase in the future.

26、LOC(lead on chip)

Lead on chip (LOC) is a structure in which the front end of the lead frame is above the chip and a bumpy solder joint is made near the center of the chip, and the electrical connection is made by stitching the leads together. Compared to the original structure where the lead frame is placed near the side of the chip, the chip can be accommodated in the same size package with a width of about 1mm.

27、LQFP (low profile quad flat package)

Thin QFP refers to a QFP with a package body thickness of 1.4mm, and is the name used by the Japan Electronics Machinery Industry Association in accordance with the new QFP form factor specifications.

28、L-QUAD

One of the ceramic QFPs. The package substrate is made of aluminum nitride, and the thermal conductivity of the base is 7 to 8 times higher than that of aluminum oxide, providing better heat dissipation. The frame of the package is made of aluminum oxide, and the chip is sealed by potting method, thus suppressing the cost. It is a package developed for logic LSI and can accommodate W3 power under natural air cooling conditions. The 208-pin (0.5mm center pitch) and 160-pin (0.65mm center pitch) packages for LSI logic have been developed and were put into mass production in October 1993.

29、MCM(multi-chip module)

Multi-chip module. A package in which multiple semiconductor bare chips are assembled on a wiring substrate. MCM-L is a component that uses the usual glass epoxy resin multilayer printed substrate. MCM-C is a component that uses thick film technology to form multilayer wiring with ceramic (alumina or glass-ceramic) as the substrate, similar to thick film hybrid ICs that use multilayer ceramic substrates. There is no significant difference between the two. MCM-D is a component that uses a thin-film technology to form multilayer wiring with ceramic (alumina or aluminum nitride) or Si or Al as the substrate. The wiring density is the highest among the three types of components, but the cost is also high.

30、MFP(mini flat package)

Small flat package. An alias for plastic SOP or SSOP (see SOP and SSOP). The name used by some semiconductor manufacturers.

31、MQFP(metric quad flat package)

A classification of QFPs according to the JEDEC (Joint Electronic Devices Committee) standard. It refers to the standard QFP with a pin center distance of 0.65mm and a body thickness of 3.8mm to 2.0mm (see QFP).

32、MQUAD (metal quad)

A QFP package developed by Olin, USA. The substrate and cover are made of aluminum and sealed with adhesive. It can accommodate 2.5W to 2.8W of power under natural air-cooling conditions. It was licensed by Nihon Kohki Kogyo in 1993 and started production.

33、MSP(mini square package)

QFI alias (see QFI), in the early stage of development, mostly called MSP, QFI is the name prescribed by the Japan Electronics Machinery Industry Association.

34、OPMAC(over molded pad array carrier)

Over molded resin sealed bump display carrier. The name used by Motorola for molded resin sealed BGA (see BGA).

35、P-(plastic)

Indicates the mark of plastic package. For example, PDIP means plastic DIP.

36、PAC(pad array carrier)

Bump display carrier, alias of BGA (see BGA).

37、PCLP(printed circuit board leadless package)

Printed circuit board leadless package. The name adopted by Fujitsu Japan for the plastic QFN (plastic LCC) (see QFN). The pin center distance is 0.55mm and 0.4mm. Currently in the development stage.

38、PFPF(plastic flat package)

Plastic flat package. Alias for plastic QFP (see QFP). The name used by some LSI manufacturers.

39、PGA(pin grid array)

Pin array package. A cartridge-type package in which the vertical pins on the bottom side are arranged in a display pattern. Basically, multilayer ceramic substrates are used for the package substrate. In the absence of a specific material name, most are ceramic PGAs, which are used for high-speed, large-scale logic LSI circuits. The cost is high. Pin centers are typically 2.54mm apart and pin counts range from 64 to about 447. To reduce the cost, the package substrate can be replaced by a glass epoxy printed substrate. There are also plastic PG A with 64 to 256 pins, and there is also a short pin surface mount PGA with 1.27mm pin center distance (touch-solder PGA). (See surface mount type PGA).

40、piggy back

Packaged package. A ceramic package with a socket, similar in shape to DIP, QFP, and QFN. Used in the development of devices with microcomputers to evaluate program verification operations. For example, the EPROM is inserted into the socket for debugging. This package is basically a custom product and is not widely available on the market.

41、PLCC(plastic leaded chip carrier)

Plastic chip carrier with leads. One of the surface mount packages. The pins are led from the four sides of the package, in the shape of a ding, is a plastic product. It was first adopted by Texas Instruments in the United States for 64k-bit DRAM and 256k DRAM, and is now commonly used for logic LSI, DLD (or process logic device), and other circuits. The pin center distance is 1.27mm and the number of pins ranges from 18 to 84. J-shaped pins are less deformable and easier to handle than QFP, but it is more difficult to check the appearance after soldering. 

PLCC is similar to LCC (also called QFN). Previously, the only difference between the two was that the former was made of plastic and the latter was made of ceramic. However, there are now J-shaped packages made of ceramic and pinless packages made of plastic (marked as plastic LCC, PC LP, P-LCC, etc.), which are indistinguishable. For this reason, the Japan Electronics and Machinery Industry Association decided in 1988 to call packages with J-shaped pins leading from all four sides QFJs and packages with electrode bumps on all four sides QFNs (see QFJ and QFN).

42、P-LCC(plastic teadless chip carrier)(plastic leaded chip currier)

Sometimes it is an alias for plastic QFJ, sometimes it is an alias for QFN (plastic LCC) (see QFJ and QFN). Some LSI manufacturers use PLCC for leaded package and P-LCC for leadless package to show the difference.

43、QFH(quad flat high package)

Quad flat package with thick pins. A type of plastic QFP in which the body of the package is made thicker to prevent breakage of the package body (see QFP). The name used by some semiconductor manufacturers.

44. QFI (quad flat I-leaded packgac)

Quad flat I-leaded package. One of the surface mount type packages. The pins are led from the four sides of the package, downward in an I-word. Also called MSP (see MSP). The mount is touch-soldered to the printed substrate. This package was developed and used by Hitachi for video analog ICs. This package is also used in Motorola's PLL ICs in Japan. The pin center distance is 1.27mm, and the number of pins ranges from 18 to 68.

45、QFJ(quad flat J-leaded package)

Quad flat J-leaded package. One of the surface mount packages. The pins are led from the four sides of the package in a downward J-shape. This is the name specified by the Japan Electrical and Mechanical Manufacturers Association. The pin center distance is 1.27mm.

There are two types of materials: plastic and ceramic. Plastic QFJs are mostly called PLCCs (see PLCC) and are used in circuits such as microcomputers, gate displays, DRAMs, ASSPs, OTPs, etc. Pin counts range from 18 to 84.

Ceramic QFJs are also known as CLCC, JLCC (see CLCC). Windowed packages are used for UV-erasable EPROMs and microcomputer chip circuits with EPROMs. Pin counts range from 32 to 84.

46、QFN(quad flat non-leaded package)

Quad flat non-leaded package. One of the surface mount packages. Nowadays, it is mostly called LCC, and QFN is the name specified by the Japan Electronics and Machinery Industry Association. The package is equipped with electrode contacts on all four sides, and because it has no pins, the mounting area is smaller than QFP and the height is lower than QFP.

However, when stress is generated between the printed substrate and the package, it cannot be relieved at the electrode contacts. Therefore, the number of electrode contacts is not as large as the number of pins in QFP, generally from 14 to about 100. There are two types of materials: ceramic and plastic. Ceramic QFNs are basically used when LCC markings are present, and the electrode contact centers are 1.27 mm apart.

Plastic QFN is a low cost package with a glass epoxy printed substrate. In addition to 1.27mm, there are 0.65mm and 0.5mm electrode contact center distances. This package is also called plastic LCC, PCLC, P-LCC, etc.

47、QFP(quad flat package)

Quad flat package. One of the surface mount package, the pins are led from four sides in a seagull wing (L) shape. There are three types of substrates: ceramic, metal and plastic. In terms of quantity, plastic packages make up the majority. Plastic QFP is the most popular multi-pin LSI package. They are used not only for digital logic LSI circuits such as microprocessors and gate displays, but also for analog LSI circuits such as VTR signal processing and audio signal processing. The maximum number of pins in the 0.65mm center distance specification is 304.

In Japan, QFPs with a pin center distance of less than 0.65mm are called QFPs (FP). However, the Japan Electrical and Mechanical Manufacturers' Association has now re-evaluated the form factor of QFPs. Instead of differentiating the pin center distance, the package body is divided into QFP (2.0mm to 3.6mm thick), LQFP (1.4mm thick), and TQFP (1.0mm thick) according to the package body thickness.

Some LSI manufacturers call QFPs with 0.5mm pin centers a shrink type QFP or SQFP or VQFP, while others call QFPs with 0.65mm and 0.4mm pin centers an SQFP, making the names slightly confusing.
To prevent pin distortion, several improved QFP variants have been developed. For example, the BQFP (see BQFP), which has finger cushions on all four corners of the package; the GQFP (see GQFP), which has a protective resin ring covering the front of the pins; and the TPQFP (see TPQFP), which has test bumps in the package body and can be tested in a special fixture to prevent pin deformation. 

For logic LSIs, many development and high-reliability products are packaged in multilayer ceramic QFPs. Products with a minimum pin center distance of 0.4mm and a maximum pin count of 348 are also available. Ceramic QFPs with glass seals are also available (see Gerqa d).

48. QFP (FP) (QFP fine pitch)

QFP fine pitch is the name specified in the JEM standard. It refers to QFPs with a pin center distance of 0.55mm, 0.4mm, 0.3mm, etc. less than 0.65mm (see QFP).

49、QIC (quad in-line ceramic package)

Alias for ceramic QFP. The name used by some semiconductor manufacturers (see QFP, Cerquad).

50、QIP (quad in-line plastic package)
Alias for plastic QFP. The name used by some semiconductor manufacturers (see QFP).

51、QTCP(quad tape carrier package)

One of the TCP packages in which pins are formed on an insulating tape and lead out from all four sides of the package. It is a thin package using TAB technology (see TAB, TCP).

52、QTP(quad tape carrier package)

Quad tape carrier package. The name used in the form factor specifications for QTCP established by the Japan Electrical Machinery Manufacturers Association in April 1993 (see TCP).

53、QUIL(quad in-line)
The alias of QUIP (see QUIP).

54, QUIP (quad in-line package)

Quad in-line package with four rows of pins. The pins are led from two sides of the package, and every other one is staggered and bent down into four rows. The pin center distance is 1.27mm, when inserted into the printed substrate, the insertion center distance becomes 2.5mm, so it can be used in standard printed circuit boards. It is a smaller package than the standard DIP. NEC uses these packages for microcomputer chips in desktop computers and home appliances. There are two types of materials: ceramic and plastic. The number of pins is 64.

55、SDIP (shrink dual in-line package)

One of the cartridge packages, the shape is the same as DIP, but the pin center distance (1.778 mm) is smaller than that of DIP (2.54 mm).

Hence the name. The number of pins ranges from 14 to 90, and is also called SH-DIP. There are two types of materials: ceramic and plastic.

56、SH-DIP (shrink dual in-line package)

The same as SDIP, the name used by some semiconductor manufacturers.

57、SIL(single in-line)
The alias of SIP (see SIP). The name SIL is mostly used by European semiconductor manufacturers.

58、SIMM (single in-line memory module)

Single in-line memory module. A memory module with electrodes near only one side of the printed substrate. Usually refers to the component that is inserted into a socket. Standard SIMMs are available with 30 electrodes at 2.54mm center distance and 72 electrodes at 1.27mm center distance. SIMMs with 1 and 4 megabit DRAMs in SOJ packages on one or both sides of a printed substrate are widely used in personal computers, workstations, and other devices. At least 30-40% of DRAMs are assembled in SIMMs.

59、SIP(single in-line package)
Single in-line package. The pins are led out from one side of the package and arranged in a straight line. When assembled on a printed substrate, the package is in a side-standing position. The pin center distance is typically 2.54mm and the number of pins ranges from 2 to 23, with most custom products. The shape of the package varies. Some packages with the same shape as ZIP are also called SIP.

60、SK-DIP (skinny dual in-line package)
A type of DIP. It refers to the narrow body DIP with a width of 7.62mm and a pin center distance of 2.54mm, which is usually referred to as DIP (see DIP).

61、SL-DIP (slim dual in-line package)
A type of DIP. It refers to the narrow DIP with a width of 10.16mm and a pin center distance of 2.54mm.

62、SMD(surface mount devices)
Surface mount devices. Occasionally, some semiconductor manufacturers classify SOP as SMD (see SOP).

63、SO(small out-line)
SOP alias. This alias is used by many semiconductor manufacturers around the world. (See SOP).

64、SOI(small out-line I-leaded package)
I-shaped pin small out-line package. One of the surface mount packages. The pins are led downward from both sides of the package in an I-shape with a center distance of 1.27mm, and the mounting area is smaller than that of SOP. Number of pins 26.

65、SOIC(small out-line integrated circuit)
An alias for SOP (see SOP). Many foreign semiconductor manufacturers have adopted this name.

66、SOJ (Small Out-Line J-Leaded Package)
J-shaped pin small outline package. One of the surface mount package. The pins are led downward from both sides of the package in a J shape, so it is named. Most of the DRAM devices in SOJ packages are assembled on SIMMs. The pin center distance is 1.27mm and the number of pins ranges from 20 to 40 (see SIMM).

67、SQL(Small Out-Line L-leaded package)
The name used for SOPs according to the JEDEC (Joint Electronic Device Engineering Council) standard (see SOP).

68、SONF(Small Out-Line Non-Fin)
This is the same as the usual SOP. The NF (non-fin) designation was intentionally added to indicate the difference between a power IC package without a heat sink. The name used by some semiconductor manufacturers (see SOP).

69、SOF(small Out-Line package)
Small Outline Package. One of the surface mount package, the pins are led from both sides of the package in the shape of seagull wings (L-shaped). There are two types of materials: plastic and ceramic. Also known as SOL and DFP.

SOPs are used for memory LSIs as well as for less large circuits such as ASSPs. SOP is the most popular surface mount package in the field where the input and output terminals do not exceed 10 to 40. The pin center distance is 1.27mm, and the number of pins ranges from 8 to 44.
In addition, SOPs with pin center distance less than 1.27mm are also called SSOPs; SOPs with assembly height less than 1.27mm are also called TSOPs (see SSOP, TSOP). There is also a SOP with a heat sink.

70、SOW (Small Outline Package (Wide-Jype))
A name used by some semiconductor manufacturers.